1. Field of the Invention
The present invention relates to a Viterbi detector that uses best state information to control a path memory.
2. Description of the Prior Art
The use of Viterbi detectors has increased with increased sophistication of integrated circuits, allowing for this detection technique to be used in a wide variety of applications. For example, wireless cellular phones and various forms of digital television broadcasting now can economically gain an improvement in signal-to-noise ratio at the detector stage by the use of the Viterbi technique. The Viterbi technique has recently been employed with magnetic disk drives, in order to better recover a desired data signal in the presence of various forms of noise and distortion due to the nature of the magnetic recording media. The Viterbi technique has proven especially valuable when used with magneto-resistive (MR) recording heads used with various partial-response (PR) detection schemes.
A typical magnetic disk-drive implementation using a fourth-order PR detector, referred to as "EPR4", and the associated control loops is shown in FIG. 1. This implementation has two control loops: the first includes a phase-locked loop (PLL) 111 to generate a recovered clock to control the sampling of the data pulses read from the magnetic medium (e.g., rotating disk), and the second includes an integrator to control the gain of a variable gain amplifier (VGA) 101. Referring first to the main signal path, the input signal, illustratively from a magnetic read head 100, is supplied to the VGA (101), the output of which is applied to the continuous time filter 102, which provides a degree of equalization. The output of filter 102 is sampled by sampler 103 and supplied to equalizer 104, which may supply an additional degree of phase equalization if desired, so that combined effects of the original pulse shape and all equalization produce the partial response known as PR4. The equalized signal is then supplied to the analog-to-digital (A/D) converter 105, the output of which is supplied to a 1+D filter 106 via node 114. The 1+D filter 106 serves to convert the PR4 equalized signal to an EPR4 equalized signal, and supplies the filtered signal to the Viterbi detector 107, which selects the most likely value of the signal and supplies a "final" output signal on line 120 to other portions of the disk drive circuitry, typically providing for decoding, error recovery, etc. In the illustrative case, the Viterbi detector provides the EP4 partial response, but other partial response functions may be implemented with Viterbi detectors of appropriate design.
The path to the control loops includes a symbol-by-symbol slicer 108, which selects one of three possible levels (-1, 0 and +1) in the illustrative case of equalization to the PR4 response, which has a three-level eye diagram. The slicer 108 supplies its preliminary decisions to a summer 109. Note that "preliminary" as used herein means that the decision is performed before the final output of the Viterbi detector 107. Therefore, the preliminary decision may be somewhat less accurate, but is obtained more quickly than the final decision. The summer 109 also receives an input representing the signal from node 114 on line 115, in order to form an error signal on line 116, which is supplied both the phase (.phi.) error detector 110 and the gain error detector 112. The preliminary decision is also supplied to the phase error detector 110 and the gain error detector 112. The output of the phase error detector 110 is supplied to the phase-locked loop 111, which supplies a recovered clock signal on line 118 for control of the sampler 103. The output of the gain error detector 112 is supplied to the integrator 113, which supplies a gain control signal on line 119 to the VGA 101. As thus described, these control loops are conventional in the art.
In some non-disk drive applications with very low loop bandwidths, a control loop could be supplied with the "final decision" from the Viterbi detector. This would improve the accuracy of the control signal, but would delay it in time due to the delay through the Viterbi detector. This delay may lead to a loss in effective control of the desired loop, whether it be for generating a recovered clock or gain control. In order to understand this delay, note that the Viterbi technique makes use of the history of digital data samples, in order to derive the most likely value (e.g., digital "0" or "1") for a given sample. That is, by relying on a history of the samples, an improvement in signal-to-noise ratio of up to several dB is frequently possible, as compared to simply looking at the value of a single sample. This allows for a reduction in data errors, which allows for improved performance.
Maximum Likelihood detection is the optimal detection method for partial-response schemes, where the received signal is equalized into a known PR of the form: EQU a.sub.n D.sup.n +a.sub.n-1 D.sup.n-1 + . . . +a.sub.0 D.sup.0
where D is the delay operator. The Viterbi detector, which is a means of performing maximum-likelihood detection, takes the symbol-spaced samples of the equalized signal, and generates the symbol sequence that is most likely, given the sequence of the samples. For a digital implementation of this detector, the equalized samples are digitized using an AID converter, with a resolution that adds sufficiently low quantization noise. In general, the Viterbi detector has N "states", (where N.ltoreq.2.sup.n) where each state represents the last n symbols. There are transitions in the trellis diagram that connect any state to its two possible predecessor states for a binary PR with no coding constraints built into the trellis. In order to decide the most likely sequence of symbols, the Viterbi detector chooses the most likely transition based on minimizing the mean-square-error (MSE) as will be explained below. Therefore, at any given time, there is one path that ends at each state, referred to as the survivor path. PA1 1. Add state metric 010 at time k-1 to branch.sub.-- metric.sub.-- 0
Let us take the PR a.sub.3 D.sup.3 +a.sub.2 D.sup.2 +a.sub.1 D+a.sub.0, as an example to illustrate the minimum MSE criterion, where a.sub.3, a.sub.2, a.sub.1 and a.sub.0 are the coefficients that determine the partial response. This type of partial response is referred to as "EPR4" when a.sub.3 =a.sub.2 =-a.sub.1 =-a.sub.0, but is considered herein in the general fourth-order case. Still other response types are known in the art for various applications, with higher-order responses being likely in future-generation read channel designs. Consider two of 8 possible initial states, being illustratively states 010 and 110, and their transition to state 100: For the transition from state 010 to state 100 (which corresponds to a symbol sequence 0100) the ideal equalized sample would be (-a.sub.3 +a.sub.2 -a.sub.1 -a.sub.0). The error is defined as the squared difference between the received noisy sample and this ideal sample; i.e. (y.sub.n -(-a.sub.3 +a.sub.2 -a.sub.1 -a.sub.0)).sup.2. Let's call this the "branch.sub.-- metric.sub.-- 0". Similarly, for the other possible transition to the state 100 (i.e., from state 110), "branch-metric.sub.-- 1" equals (y.sub.n -(a.sub.3 +a.sub.2 -a.sub.1 -a.sub.0)).sup.2. In order to choose the most likely path to state 100, we need to choose the branch (transition) that leads to the minimum "state metric", which is the sum of the state metric of the predecessor state and the associated branch metric. That is, the state metric is the accumulated sum of the branch metrics of that path, and is also referred to herein as "SM". (The state metric is alternatively referred to as the "path metric" by workers in the art). Note that as used herein, the term "best state" refers to the sate with the lowest state metric. Hence, we need to perform the Add-Compare-Select (ACS) operation:
2. Add state metric 110 at time k-1 to branch.sub.-- metric.sub.-- 1
3. Compare the two sums. PA4 4. Select the sum with the lower state metric and update state metric of state 100.
In an illustrative prior-art case, an eight-state Viterbi detector includes eight ACS circuits having eight decision outputs that are provided to a path memory. The path memory is used to process the decisions made by all of the states so that each segment of the path memory (associated with a particular state) contains a candidate data sequence, which is correct if that particular state is actually the correct state. The information in the path memory can be thought of as a tree structure. The depth of the path memory (in the prior art) must be sufficient to ensure that when a final decision is made by tracing back starting from an arbitrary terminal (or leaf) of the tree, the same root, resulting in the same final binary decision, is arrived at no matter which leaf is chosen as a starting point. While the required depth of the path memory depends substantially upon the particular partial response and any codes which may have been used, it is typically necessary to have a depth (and additional latency) between 12 and 20 bit long. Therefore, it can be seen that the path memory adds significant delay in reaching the final decision.
While the circuitry of FIG. 1 is suitable for implementing PR4 and EPR4 partial responses, higher-order partial responses that are used with magnetic media will use other circuit implementations. This higher-order partial responses will produce an even larger difference between the preliminary decision obtained by the above technique and the final decision. Therefore, what is needed is a method of producing accurate, low-latency preliminary decisions that can be used for high-order partial response Viterbi detectors.